1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a square oxide structure or a square floating gate structure without a rounding effect at the corners of the square oxide structure or the square floating gate structure.
2) Description of the Prior Art
The use of a silicon nitride layer as an oxidation mask is well known. To form square structures, such as oxide isolation structures or floating gates in a split cell memory, a photosensitive mask is formed with square openings, and the silicon nitride layer is etched through these openings.
However, due to limitations of the photolithography process, the corners of square openings in the photosensitive mask become rounded. This rounding of the corners of a square opening in a photosensitive mask is known as a rounding effect. As device dimensions continue to shrink, this rounding effect at the corners of square structures can have a detrimental effect on device performance. This detrimental effect can be worse when mis-alignment between photolithography masks occurs.
Another problem which occurs as packing density increases, is that the gap between floating gates in a split cell memory device is limited by the photolithography process. After a polysilicon layer is formed, openings (or gaps) are etched to define and separate floating gates. The width of the opening in the photosensitive or silicon nitride etch mask is limited by parameters of the photolithography process such as wavelength of the energy source, resolution, and aspect ratio.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,879,992 (Hsieh et al.) shows a flash split gate memory using a poly oxide hard mask to etch an underlying floating gate in an underlying polysilicon layer.
U.S. Pat. No. 5,858,940 (Hsieh et al.) discloses a flash cell split gate memory using a poly oxide hard mask with a sharp tip for etching a floating gate in an underlying polysilicon layer.
U.S. Pat. No. 5,780,341 (Ogura) shows a method for forming an EPROM having an STI.
U.S. Pat. Nos. 5,364,806 (Ma et al.) and 5,811,853 (Wang) disclose other methods for forming flash split gate memories.